![]() Memory_array top3(data_out, data_in, clk,fifo_we, wptr,rptr) Read_pointer top2(rptr,fifo_rd,rd,fifo_empty,clk,rst_n) Write_pointer top1(wptr,fifo_we,wr,fifo_full,clk,rst_n) Output fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow Input data_in // FPGA projects using Verilog/ VHDL output data_out : FPga projects, Verilog projects, VHDL projects // Verilog project: Verilog code for FIFO memory // Top level Verilog code for FIFO Memory module fifo_mem(data_out,fifo_full, fifo_empty, fifo_threshold, fifo_overflow, fifo_underflow,clk, rst_n, wr, rd, data_in) ![]()
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